Dissipated Power Reduction in Domino Circuit

In this paper we have analyzed the advantages of using dynamic circuits over static circuits with result oriented example for NAND operation. The different aspects covered under this discussion include power, speed, area, input Capacitance and timing delays calculation. We have also covered the problem of increase in dynamic power dissipation at the dynamic and the output node in dynamic circuits. A circuit is proposed for unfooted dynamic buffer circuit where the power dissipation is reduced from 256μW to 142μW at the output node in the proposed circuit as compared to that in standard dynamic domino logic buffer circuit. Simulation results are obtained using 0.12μm CMOS technology.